1. Field of the Invention
The present invention relates to a protective circuit for protecting a semiconductor integrated circuit from electrostatic discharge, and more specifically to a protective circuit that can reduce a mounting area by decreasing the number of elements.
2. Background Art
A protective circuit is used for protecting semiconductor integrated circuits from electrostatic discharge (ESD) (for example, refer to Patent Documents 1 to 6). The protective circuit is connected between a power source terminal or input-output terminal of the semiconductor integrated circuit and GND. The protective circuit is composed of, for example, a plurality of stages of diodes connected in series so as not to operate at a certain voltage or below. In the protective circuit for the power source terminal, the number of stages of diodes is determined so as not to operate at a power-source voltage or below. On the other hand, in the protective circuit for the input-output terminal, the number of stages of diodes is determined so as not operate at the voltage amplitude of normal input-output power.
[Patent Document 1] Japanese Patent Laid-Open No. 6-104712
[Patent Document 2] Japanese Patent Laid-Open No. 10-274663
[Patent Document 3] Japanese Patent Laid-Open No. 10-164748
[Patent Document 4] Japanese Patent Laid-Open No. 58-58827
[Patent Document 5] Japanese Patent Laid-Open No. 5-36979
[Patent Document 6] Japanese Patent Laid-Open No. 64-55017